This invention relates generally to a semiconductor memory, and more particularly relates to an arrangement which is advantageous for use in a dynamic type RAM (Random Access Memory) which contains a stand-by memory array.
In semiconductor memories such as dynamic type RAMS and so on a stand-by memory array can be prepared ahead of time in the memory array. The stand-by memory acts to be shifted as an alternative to a word line or a data line in which a defective memory cell is detected within the memory array. Thus, an operation which can be called a defective bit relief is carried out for the purpose of keeping a high product yield. In order to achieve this object, a redundant address switching circuit is provided which memorizes the defective address, compares this defective address with an address signal which is supplied from outside at the time of memory accessing, and switches the defective address for an address in the stand-by memory array when this defective address is assigned.
A dynamic type RAM containing such a redundant address switching circuit is, for example, shown at P.P 209 to P.P 231, "Nikkei Electronics", issued on June 3, 1985, published by Nikkei McGraw-Hill.
One address comparison type device is an arrangement in which a comparison address is provided by way of whether the fuse of an address comparison circuit having a programming element such as a fuse is melted or not. The provided comparison address and an input address are compared with each other so as to form a redundant address switching signal. Such an arrangement has been conventionally used (e.g., see P. 239 to P. 245, No. 239 Edition, "Nikkei Electronics", issued on Feb. 7, 1981, published by Nikkei McGraw-Hill).
In such a dynamic type RAM having the above redundant address switching circuit, a defective memory cell is detected at the time of checking products, and the address of the word line or a data line to which the defective memory cell is connected is registered in a ROM (Read Only Memory) of the redundant address switching circuit. When this defective address is then assigned, an address aligning signal of an address comparison circuit which is contained in the redundant address switching circuit is output, and switching for the corresponding stand-by memory array is thus carried out. An address roll mechanism is used which outputs an address aligning signal of the address comparison circuits which respectively corresponds to each stand-by memory array. The address aligning signal is provided to the outer terminal so as to identify a row address or a column address of the word line or a data line to which the defective memory cell is connected.